1. Field of the Invention
The present invention generally relates to a current source apparatus. More particular, the present invention relates to a current source apparatus with bias switches appropriate for application to digital-to-analog converter. The output compliance and settling time performance of the current source apparatus according to the present invention is improved.
2. Description of the Related Art
Generally, in video digital-to-analog converters (video DAC hereinafter), the on and off states of current cells are controlled via decoding the digital data to supply a specific amount of output current. The output current flows through an output resistor, therefore, the video DAC outputs a corresponding analog output voltage.
FIG. 1 illustrates a block diagram of a DAC circuit. In FIG. 1, the decoder 1 decodes digital data D.sub.input and outputs control signals for controlling the on and off states of current cells 2, 3, and 4. The output current I.sub.out flowing through the output resistor R.sub.out (an equivalent load resistor connected in the output terminal of the DAC) is adjusted, and an output voltage V.sub.out is generated. By decoding different digital data, the on and off states of current cells have different combinations, and consequently different output voltages (V.sub.out) corresponding to digital data are generated via generating different output currents (I.sub.out).
FIG. 2 is a schematic diagram of a current cell 20 depicted in FIG. 1, wherein IN1 and IN2 indicate two inverters. In FIG. 2, the source of the PMOS P0 is connected to a positive voltage V.sub.DD, and the gate of PMOS P0 is biased by voltage V.sub.bias, which turns on the PMOS P0. When the current cell 20 receives decoded signal "1" (DATA), the PMOS P1 is turned on, and current I flows from V.sub.DD through PMOS P0, and P1 to output terminal IO. Accordingly, output voltage V.sub.out appears when current I flows across the output load resistor.
For video DAC, two important specifications are current output compliance and voltage settling time. In FIG. 3, another general current cell 30 is illustrated. When V.sub.DD is 5 V, the current cell 30 has good current output compliance performance, that is, the output current of the current cell 30 is not subject to dramatic interference due to a rise of output voltage. Therefore, the current source can supply steady current and the current source behaves as a fixed current source, such that the analog output of the video DAC is more accurate. The PMOS P0 and P3 work in the saturation region, and the resistance of output resistor r0 and r3 is quite high, therefore, the equivalent output resistance at terminal IO equal to r0 in series with r3 is high enough such that the output current of the current source is not subject to variation due to the variation of the output voltage.
To conserve power consumption and achieve fast operation for VLSI, the operating voltage is reduced from 5 V to 3.3 V or even lower. This degrades the current output compliance and operation speed performance for a current source.
In FIG. 3, provided the absolute values .vertline.V.sub.th .vertline. of the threshold voltages of PMOS P0 and P3 are about 0.8 V, the power source V.sub.DD is 3.3 V. To keep PMOS P0 turned-on, V.sub.bias can not exceed 2.5 V. If V.sub.bias is 2.5 V, then the voltage V.sub.A1 at node A1 is about 2.7 V, while P0 is turned on. To keep PMOS P3 turned-on, V.sub.bias2 can not exceed 1.9 V. Accordingly, the current flows from V.sub.DD node through P0, P3, and P1 to output terminal IO. However, when the output voltage V.sub.IO at output terminal IO exceeds about 1.1 V, it is obvious that PMOS P3 will operate in a non-saturation region. The output resistor r3 is reduced, such that the output resistor at output terminal IO is also reduced. Consequently, the output current of the current cell 30 is reduced due to the rise of output voltage, resulting in serious deterioration of the current output compliance performance. In addition, the settling time for output voltage is also increased due to unstable current output.
In order to improve the current output compliance performance, voltages V.sub.bias and V.sub.bias2 are raised, and thus voltage at node C1 is raised. The drain current is I=K.times.(W/L).times.(V.sub.gs -V.sub.th).sup.2, wherein K is a constant, and W and L are the width and length of the channel of PMOS, respectively. This increase of the voltage at C1 node will reduce the output current. To overcome the drawbacks, the areas of PMOS P0 and P3 are increased, that is, the value of W/L is increased, thereby increasing the output current. However, the parasitic capacitance at A1 and C1 nodes is increased, resulting in voltage coupling to C1 node due to voltage switching (DATA or DATAB is switched between "1" and "0") in the gates of P1 and P2. The output current is subject to switching noise and becomes unstable. In addition, the operating speed is degraded such that the settling time is increased.